WAND Network Research Group University of Waikato Crest Of Arms


Highly accurate synchronization of computer clocks is critical for many applications, such as air traffic control and high-frequency trading. Microprocessor based Network Time Protocol (NTP) servers suffer from a large amount of timestamp jitter, due to the hardware and Operating System (OS) being shared among other applications. The goal of this project is to implement a stratum-1 NTP server in reconfigurable logic that is capable of Gigabit Ethernet linerates with less than 8 ns of jitter.


The hardware platform for this project is the Zedboard produced by Avnet. These boards are based around the Xilinx Zynq-7000 SoC which provides a dual-core ARM processing system and FPGA programmable logic in one package. The Zedboards have an onboard Gigabit ethernet connection, however, It is not possible to route this directly into the programmable logic so an ethernet daughter board is required to achieve the necessary performance for the NTP server.


The ARM core in the Zynq-7000 allows the board to run Linux which can communicate with the NTP server running on programmable logic through a simple custom driver. This driver allows for parameters to be set on the server and for the logging of NTP activities to be handled by the Linux installation as with a regular software implementation of an NTP server. This driver controls the NTP server by reading and writing values to a set of control registers instantiated within the NTP core using memory mapped IO. The second function of this driver is to handle the logging of the data generated by the NTP server. To do this, the driver provides several buffers in it's memory space to the NTP server which the FPGA dumps its data to directly. When a buffer is full, the FPGA fires an interrupt and moves onto the next buffer. The interrupt is handled by the driver and the full buffer is dumped to the file system. Linux can be installed and booted from the onboard SD card by following the instructions here


The device driver to control the FPGA NTP server is setup as a character device. Thus parameters can be set or retrieved by simply writing to this file once the driver kernel module has been inserted. The various registers and their position within the file is outlined in the table below. For example, if one wanted to set the IPv6 address for the NTP server, they would open the device file, scan to the 16th byte and write a 16 byte value from that position.

FPGA Register layout:
0 Bytes				 8 Bytes			         16 Bytes
|		Time		   |		     Addend		     |
|				   |					     |
| 	   		   	  IPv6	                                     |
|				   					     |
|    IPv4       |      Port        |                   MAC                   |
|	        |		   |       	                             |
| 	   Buffer 1                |	            Buffer 2                 |
|          Mem. Addr	 	   |		    Mem. Addr                |
|    Buffer     |                                                            |
|    Length     |                                                            |
  • Time:
    • 64-bit value used to set the current time of the NTP server

  • Addend:
    • 64-bit value to determine how much time should increment on each clock tick

  • IPv6:
    • The IPv6 address to be used by the NTP server (128-bits)

  • IPv4:
    • The IPv4 address to be used by the NTP server (32-bits)

  • Port:
    • The port on which the server should operate (16-bits padded to 32)

  • MAC:
    • The MAC address for the network controller connected to the NTP server (48-bits padded to 64)

  • Buffer 1 & 2 Memory Address:
    • The physical memory address of the buffers used to store NTP log data (room for 32 & 64-bit pointers)

  • Buffer Length:
    • The length (in bytes) of the buffers used to store NTP log data (32-bits)


HDL Sources:

Linux Software:

Contact Details

The FPGA NTP server is written and maintained by ...